Design And Verification Engineer
OPENING FOR DIGITAL DESIGN AND VERIFICATION
JOB REQUIREMENTS
- We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.
- The person needs to have an excellent/good Verilog/SystemVerilog/Perl Skillset.The coding will be Perl mixed Verilog/SV.
- Knowledge of Make, Python, Bash is an advantage, but not mandatory.
- The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.
- The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.
BENEFITS
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Opportunity to work in complex ASIC product design from scratch.
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Opportunity to learn alongside experienced and passionate engineers.
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Monthly Stipend/Remuneration.
